               
///axi4 signal defines
typedef enum logic[1:0] {
  axi4_fixed,   axi4_incr,    axi4_wrap
} axi4_burst_e;

typedef enum logic[3:0] {
  axi4wr_dv_nb,     axi4wr_dv_b,    axi4wr_nr_ncnb,   axi4wr_nr_ncb,
  axi4wr_wt_na = 4'b0110,           axi4wr_wt_rwa = 4'b1110,
  axi4wr_wb_na = 4'b0111,           axi4wr_wb_rwa = 4'b1111
} axi4_wrcache_e;

typedef enum logic[3:0] {
  axi4ar_dv_nb,     axi4ar_dv_b,    axi4ar_nr_ncnb,   axi4ar_nr_ncb,
  axi4ar_wt_na = 4'b1010,           axi4ar_wt_rwa = 4'b1110,
  axi4ar_wb_na  = 4'b1011,          axi4ar_wb_rwa = 4'b1111
} axi4_arcache_e;

typedef enum bit[1:0] {
  axi4_privilege,   axi4_secure,    axi4_dataInst
} axi4_prot_e;

typedef enum logic[1:0] {
  axi4_okay,    axi4_exokay,    axi4_slverr,    axi4_decerr
} axi4_resp_e;

typedef enum logic[1:0] {
  axi4_non_share,   axi4_inner_share,   axi4_outer_share,   axi4_system
} axi4_domain_e;

typedef enum logic[1:0] {
  axi4_bar_respect,   axi4_bar_mem,   axi4_bar_ignore,   axi4_bar_sync
} axi4_bar_e;

typedef enum bit[2:0] {
  axi4_data_transfer,   axi4_error,     axi4_pass_dirty,   axi4_is_shared,  axi4_was_unique
} axi4_resp2_e;

typedef enum bit[3:0] {
  axi4_read_once, axi4_read_shared,   axi4_read_clean,    axi4_read_nshared,  axi4_read_unique = 4'b0111,
  axi4_clean_unique = 4'b1011,        axi4_make_unique = 4'b1100,   axi4_clean_shared = 4'b1000,
  axi4_clean_inv, axi4_make_inv,      axi4_dvm_complete = 4'b1110,  axi4_dvm_message
} axi4_arsnoop_e;

typedef enum bit[2:0] {
  axi4_write_unique,  axi4_write_line_unique,   axi4_write_clean,   axi4_write_back,  axi4_evict
} axi4_awsnoop_e;
